From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
So here we go again. Yet another attempt at making CHV watermarks sane.
This time we totally back to a memory latency based approach so that DDR DVFS
and PM5 can be enabled safely.
I also opted to follow the same path for VLV to avoid too much differences
between the platforms, and to get decent memory self refresh residency numbers.
This is now starting to resemble the ILK way of doing things quite a bit, so
hopefully that will make the eventual two stage WM update easier to achieve
on all platforms.
Ville Syrjälä (10):
drm/i915: POSTING_READ() in intel_set_memory_cxsr()
drm/i915: Split atomic wm update to pre and post variants
drm/i915: Read wm values from hardware at init on CHV
drm/i915: CHV DDR DVFS support and another watermark rewrite
drm/i915: Compute display FIFO split dynamically for CHV
drm/i915: Use the memory latency based WM computation on VLV too
drm/i915: Try to make sure cxsr is disabled around plane
enable/disable
drm/i915: Don't do PM5/DDR DVFS with multiple pipes
drm/i915: Add debugfs knobs for VLVCHV memory latency values
drm/i915: Zero unused WM1 watermarks on VLV/CHV
drivers/gpu/drm/i915/i915_debugfs.c | 24 +-
drivers/gpu/drm/i915/i915_drv.h | 30 +-
drivers/gpu/drm/i915/i915_reg.h | 25 +-
drivers/gpu/drm/i915/intel_display.c | 53 ++-
drivers/gpu/drm/i915/intel_drv.h | 18 +-
drivers/gpu/drm/i915/intel_pm.c | 708 +++++++++++++++++++++++++++--------
drivers/gpu/drm/i915/intel_sprite.c | 6 -
7 files changed, 679 insertions(+), 185 deletions(-)
--
2.3.6
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