On Mon, Jun 01, 2015 at 01:04:37PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > > Cdclk < crtc_clock is not allowed and suggests a different problem elsewhere. > > It is more robust and safe to assume no scaling is possible in this case. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 93a5e51..4c99373 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -13234,7 +13234,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state > crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; > cdclk = dev_priv->display.get_display_clock_speed(dev); Probably fallout from the in-flight dynamic cdclk stuff - this code checks the wrong bits I guess. Chandra? Thanks, Daniel > > - if (!crtc_clock || !cdclk) > + if (!crtc_clock || !cdclk || (cdclk < crtc_clock)) > return DRM_PLANE_HELPER_NO_SCALING; > > /* > -- > 2.4.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
