On Thu, Jun 11, 2015 at 04:31:16PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > The docs don't support the 64k linear scanout alignment we impose > on gen2/3. And it really makes no sense since we have no DSPSURF > register, so the only thing that the hardware will see is the linear > offset which will be just pixel aligned anyway. > > There is one case where 64k comes into the picture, and that's FBC. > The start of the line length buffer corresponds to a 64k aligned > address of the uncompressed framebuffer. So if the uncompressed fb is > not 64k aligned, the first actually used entry in the line length > buffer will not be byte 0. There are 32 extra entries in the line > length buffer to account for this extra alignment so we shouldn't > have to worry about it when mapping the uncompressed fb to the GTT. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I could not find any rationale either, and it worked this way ~10 years ago, so Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
