On Thu, Jun 04, 2015 at 06:01:35PM +0300, Imre Deak wrote:
> According to bspec the DDI PHY vswing scale value is "don't care" in
> case the scale enable bit [27] is clear. But this doesn't seem to be
> correct. The scale value seems to also matter if the scale mode bit
> [26] is set. So both bit 26 and 27 depend on the value. Setting the
> scale value to 0 while either bit is set results in a failed modeset on
> HDMI (sink reports no signal).
>
> After reset the scale value is 0x98, but according to the spec we have
> to program it to 0x9a. So for consistency program it always to 0x9a
> regardless of the scale enable bit.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
This patch successfully enables HDMI display for my team.
Tested-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 36 ++++++++++++++++++------------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 832e4e1..5246cfa 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -181,15 +181,15 @@ struct bxt_ddi_buf_trans {
> */
> static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> /* Idx NT mV diff db */
> - { 52, 0, 0, 128, true }, /* 0: 400 0 */
> - { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
> - { 104, 0, 0, 64, false }, /* 2: 400 6 */
> - { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
> - { 77, 0, 0, 128, false }, /* 4: 600 0 */
> - { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
> - { 154, 0, 0, 64, false }, /* 6: 600 6 */
> - { 102, 0, 0, 128, false }, /* 7: 800 0 */
> - { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
> + { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
> + { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
> + { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
> + { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
> + { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
> + { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
> + { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
> + { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
> + { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
> { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
> };
>
> @@ -198,15 +198,15 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> */
> static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
> /* Idx NT mV diff db */
> - { 52, 0, 0, 128, false }, /* 0: 400 0 */
> - { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
> - { 52, 0, 0, 64, false }, /* 2: 400 6 */
> - { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
> - { 77, 0, 0, 128, false }, /* 4: 600 0 */
> - { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
> - { 77, 0, 0, 64, false }, /* 6: 600 6 */
> - { 102, 0, 0, 128, false }, /* 7: 800 0 */
> - { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
> + { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
> + { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
> + { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
> + { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
> + { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
> + { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
> + { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
> + { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
> + { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
> { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
> };
>
> --
> 2.1.4
>
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--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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