On Wed, Jun 10, 2015 at 09:12:16AM +0100, Peter Antoine wrote:
> This change adds the programming of the MOCS registers to the gen 9+
> platforms. This change set programs the MOCS register values to a set
> of values that are defined to be optimal.
>
> It creates a fixed register set that is programmed across the different
> engines so that all engines have the same table. This is done as the
> main RCS context only holds the registers for itself and the shared
> L3 values. By trying to keep the registers consistent across the
> different engines it should make the programming for the registers
> consistent.
>
> v2:
> -'static const' for private data structures and style changes.(Matt Turner)
> v3:
> - Make the tables "slightly" more readable. (Damien Lespiau)
> - Updated tables fix performance regression.
>
>
> Signed-off-by: Peter Antoine <peter.antoine@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 9 ++
> drivers/gpu/drm/i915/intel_lrc.c | 68 ++++++++++
> drivers/gpu/drm/i915/intel_mocs.c | 252 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_mocs.h | 119 ++++++++++++++++++
> 5 files changed, 450 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/intel_mocs.c
> create mode 100644 drivers/gpu/drm/i915/intel_mocs.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index b7ddf48..cd7b910 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -36,7 +36,8 @@ i915-y += i915_cmd_parser.o \
> i915_trace_points.o \
> intel_lrc.o \
> intel_ringbuffer.o \
> - intel_uncore.o
> + intel_uncore.o \
> + intel_mocs.o
Please keep it alphabetical.
> # autogenerated null render state
> i915-y += intel_renderstate_gen6.o \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7213224..3a435b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7829,4 +7829,13 @@ enum skl_disp_power_wells {
> #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
> #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
>
> +/* MOCS (Memory Object Control State) registers */
> +#define GEN9_LNCFCMOCS0 (0xB020) /* L3 Cache Control base */
> +
> +#define GEN9_GFX_MOCS_0 (0xc800) /* Graphics MOCS base register*/
> +#define GEN9_MFX0_MOCS_0 (0xc900) /* Media 0 MOCS base register*/
> +#define GEN9_MFX1_MOCS_0 (0xcA00) /* Media 1 MOCS base register*/
> +#define GEN9_VEBOX_MOCS_0 (0xcB00) /* Video MOCS base register*/
> +#define GEN9_BLT_MOCS_0 (0xcc00) /* Blitter MOCS base register*/
> +
> #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 9f5485d..c875569 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -135,6 +135,7 @@
> #include <drm/drmP.h>
> #include <drm/i915_drm.h>
> #include "i915_drv.h"
> +#include "intel_mocs.h"
>
> #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
> @@ -1370,6 +1371,67 @@ out:
> return ret;
> }
>
> +/*
> + * i915_gem_program_mocs() - program the MOCS register.
> + *
> + * ring: The ring that the programming batch will be run in.
> + * ctx: The intel_context to be used.
> + *
> + * This function will emit a batch buffer with the values required for
> + * programming the MOCS register values for all the currenly supported
> + * rings.
> + *
> + * Return: 0 on success, otherwise the error status.
> + */
> +static int i915_gem_program_mocs(struct intel_engine_cs *ring,
> + struct intel_context *ctx)
Odd function name. gen8_init_mocs_tables()
> +{
> + int ret = 0;
> +
> + struct drm_i915_mocs_table t;
> + struct drm_device *dev = ring->dev;
> + struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
> +
> + if (get_mocs_settings(dev, &t)) {
Worse, this function is being pulled in from another file so needs a
proper function naem. Just return the table pointer.
> + u32 table_size;
> +
> + /*
> + * OK. For each supported ring:
> + * table_size * 2 dwords for each control_value
> + * plus table/2 dwords for l3cc values.
> + *
> + * Plus 1 for the load command and 1 for the NOOP per ring
> + * and the l3cc programming.
> + */
> + table_size = GEN9_NUM_MOCS_RINGS * ((2 * t.size) + 2) +
> + t.size + 2;
> + ret = intel_logical_ring_begin(ringbuf, ctx, table_size);
> + if (ret) {
> + DRM_ERROR("intel_logical_ring_begin failed %d\n", ret);
Error? Does this help the user in any way, especially as not enabling
mocs is not critical?
> + return ret;
> + }
> +
> + /* program the control registers */
> + emit_mocs_control_table(ringbuf, &t, GEN9_GFX_MOCS_0);
> + emit_mocs_control_table(ringbuf, &t, GEN9_MFX0_MOCS_0);
> + emit_mocs_control_table(ringbuf, &t, GEN9_MFX1_MOCS_0);
> + emit_mocs_control_table(ringbuf, &t, GEN9_VEBOX_MOCS_0);
> + emit_mocs_control_table(ringbuf, &t, GEN9_BLT_MOCS_0);
So why are programming other rings on RCS without explicit inter-engine
ordering?
> +
> + /* now program the l3cc registers */
> + emit_mocs_l3cc_table(ringbuf, &t);
> +
> + intel_logical_ring_advance(ringbuf);
> +
> + DRM_INFO("MOCS: Table set in Context\n");
> + } else {
> + DRM_INFO("MOCS: Table Not supported on platform\n");
Info? Just debug, these are not helpful user messages.
> + }
> +
> + return ret;
> +}
> +
> +
> static int gen8_init_rcs_context(struct intel_engine_cs *ring,
> struct intel_context *ctx)
> {
> @@ -1379,6 +1441,12 @@ static int gen8_init_rcs_context(struct intel_engine_cs *ring,
> if (ret)
> return ret;
>
> + /*
> + * Failing to program the MOCS is non-fatal.The system will not
> + * run at peak performance. So generate a warning and carry on.
> + */
> + WARN_ON(i915_gem_program_mocs(ring, ctx) != 0);
Warn? Just NOTICE since it is not a useful user error message and a
non-critical error to boot.
> return intel_lr_context_render_state_init(ring, ctx);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> new file mode 100644
> index 0000000..841932a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -0,0 +1,252 @@
> +/*
> + * Copyright (c) 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions: *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + * Authors:
> + * Peter Antoine <peter.antoine@xxxxxxxxx>
We don't encourage Authors: since git does a better job.
> + */
> +
> +#include "intel_mocs.h"
> +#include "intel_lrc.h"
> +#include "intel_ringbuffer.h"
> +
> +/*
> + * MOCS tables
> + *
> + * These are the MOCS tables that are programmed across all the rings.
> + * The control value is programmed to all the rings that support the
> + * MOCS registers. While the l3cc_values are only programmed to the
> + * LNCFCMOCS0 - LNCFCMOCS32 registers.
> + *
> + * NOTE: These tables MUST start with being uncached {0,0} and the
> + * the length MUST be less than 63 as the last two registers are
> + * reserved by the hardware.
> + */
> +struct drm_i915_mocs_entry skylake_mocs_table[] = {
static const ...
> + /* {0x00000009, 0x0010} */
> + {(MOCS_CACHEABILITY(EDRAM_UC) | MOCS_TGT_CACHE(LLC_ELLC) |
> + MOCS_LRUM(0) | MOCS_AOM(0) | MOCS_LECC_ESC(0) | MOCS_SCC(0) |
> + MOC_PFM(0) | MOCS_SCF(0)),
> + (MOCS_ESC(0) | MOCS_SCC(0) | MOCS_L3_CACHEABILITY(L3_UC))},
Whitespace and alignment should be treated as our friends and not
enemies.
#define SKYLAKE_MOCS(cache, ellc, lrum, l3) { \
(MOCS_CACHEABILITY(cache) | \
MOCS_TGT_CACHE(ellc) | \
MOCS_LRUM(lrum) | \
MOCS_AOM(0) | \
MOCS_LECC_ESC(0) | \
MOCS_SCC(0) | \
MOC_PFM(0) | \
MOCS_SCF(0))), \
(MOCS_ESC(0) | \
MOSC_SCC(0) | \
MOCS_L3_CACHEABILITY(l3)) \
}
would help clarify these even further, or at the very least being
consistent in layout of the tables would improve readiblity and being
able to cross-check.
> +
> +/**
> + * get_mocs_settings
> + *
> + * This function will return the values of the MOCS table that needs to
> + * be programmed for the platform. It will return the values that need
> + * to be programmed and if they need to be programmed.
> + *
> + * If the return values is false then the registers do not need programming.
> + */
> +bool get_mocs_settings(struct drm_device *dev,
> + struct drm_i915_mocs_table *table) {
const struct drm_i915_mocs_table *
gen8_lookup_mocs_table(struct drm_i915_private *i915);
> +/**
> + * emit_mocs_control_table() - emit the mocs control table
> + * @ringbuf: DRM device.
> + * @table: The values to program into the control regs.
> + * @reg_base: The base for the Engine that needs to be programmed.
> + *
> + * This function simply emits a MI_LOAD_REGISTER_IMM command for the
> + * given table starting at the given address.
> + *
> + * Return: Nothing.
> + */
> +void emit_mocs_control_table(struct intel_ringbuffer *ringbuf,
> + struct drm_i915_mocs_table *table,
> + u32 reg_base)
gen8_emit_mocs_table(...)
etc
> +/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> +#define MOCS_CACHEABILITY(value) ((value & 0x03) << 0)
value & mask? These macros should only be feed enums so the masking of
the input is superfluous and indicative of a programming bug.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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