On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote: > Due to RTL Bug, GAM does not support enabling GTT cache when > big pages are also turned on. This leads to GAM reporting > incorrect data and address. We don't use big pages, so we can leave GTT caching enabled until we support them (which may be never?). -- Damien > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0f72c0e..13474f3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -157,6 +157,9 @@ > #define GEN8_RPCS_EU_MIN_SHIFT 0 > #define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) > > +#define GEN8_GTT_CACHE_EN 0x4024 > +#define GEN8_GTT_CACHE_DEFAULT 0xf0007fff > + > #define GAM_ECOCHK 0x4090 > #define BDW_DISABLE_HDC_INVALIDATION (1<<25) > #define ECOCHK_SNB_BIT (1<<10) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b0fd5ec..dbb7059 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6285,6 +6285,9 @@ static void haswell_init_clock_gating(struct drm_device *dev) > I915_WRITE(CHICKEN_PAR1_1, > I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); > > + /* WaGttCachingOffByDefault:bdw */ > + I915_WRITE(GEN8_GTT_CACHE_EN, GEN8_GTT_CACHE_DEFAULT); > + > lpt_init_clock_gating(dev); > } > > -- > 2.1.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
