On Wed, 03 Jun 2015, Damien Lespiau <damien.lespiau@xxxxxxxxx> wrote: > On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: >> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> >> MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode >> must be applied using LRIs on gen8. >> >> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx> Thanks, pushed all patches to drm-intel-next-queued. BR, Jani. > > -- > Damien > >> --- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++-- >> 1 file changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> index 06f4b22..b70d25b 100644 >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> @@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) >> >> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); >> >> + /* WaDisableAsyncFlipPerfMode:bdw */ >> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); >> + >> /* WaDisablePartialInstShootdown:bdw */ >> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, >> @@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) >> >> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); >> >> + /* WaDisableAsyncFlipPerfMode:chv */ >> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); >> + >> /* WaDisablePartialInstShootdown:chv */ >> /* WaDisableThreadStallDopClockGating:chv */ >> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, >> @@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring) >> * to use MI_WAIT_FOR_EVENT within the CS. It should already be >> * programmed to '1' on all products. >> * >> - * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv >> + * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv >> */ >> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) >> + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) >> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); >> >> /* Required for the hardware to program scanline values for waiting */ >> -- >> 2.3.6 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
