On Wed, 03 Jun 2015 09:49:43 +0300 Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> wrote: > On Wed, 03 Jun 2015, Ben Widawsky <benjamin.widawsky@xxxxxxxxx> wrote: > > in > > commit 65ca7514e21adbee25b8175fc909759c735d00ff > > Author: Damien Lespiau <damien.lespiau@xxxxxxxxx> > > Date: Mon Feb 9 19:33:22 2015 +0000 > > > > drm/i915/skl: Implement WaBarrierPerformanceFixDisable > > > > The workaround ended up in the chv workarounds. Not sure what the > > reason or history of that is, but it /seems/ wrong. Don't know if > > this fixes anything since I have many other problems with my > > platform. > > > > Cc: Damien Lespiau <damien.lespiau@xxxxxxxxx> > > Cc: Nick Hoath <nicholas.hoath@xxxxxxxxx> > > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > > Ville beat you to it [1]. However he put it in skl workarounds, not > gen9, so I'm presuming this does not apply to bxt. > > BR, > Jani. > > Anyone who will talk to us and tells you they know the answer to that definitively is lying. My patch is wrong though. Checking only the REVID without checking IS_SKYLAKE is not the right thing to do. Consider Ville's patch Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx> (I no longer subscribe to intel-gfx, so actually adding my review is kind of a pain). > [1] > http://mid.gmane.org/1433248657-4509-1-git-send-email-ville.syrjala@xxxxxxxxxxxxxxx > > > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > > b/drivers/gpu/drm/i915/intel_ringbuffer.c index d934f85..0fd6033d > > 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -901,13 +901,6 @@ static int chv_init_workarounds(struct > > intel_engine_cs *ring) GEN6_WIZ_HASHING_MASK, > > GEN6_WIZ_HASHING_16x4); > > > > - if (INTEL_REVID(dev) == SKL_REVID_C0 || > > - INTEL_REVID(dev) == SKL_REVID_D0) > > - /* WaBarrierPerformanceFixDisable:skl */ > > - WA_SET_BIT_MASKED(HDC_CHICKEN0, > > - HDC_FENCE_DEST_SLM_DISABLE | > > - HDC_BARRIER_PERFORMANCE_DISABLE); > > - > > return 0; > > } > > > > @@ -972,6 +965,13 @@ static int gen9_init_workarounds(struct > > intel_engine_cs *ring) tmp |= > > HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; > > WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); > > + if (INTEL_REVID(dev) == SKL_REVID_C0 || > > + INTEL_REVID(dev) == SKL_REVID_D0) > > + /* WaBarrierPerformanceFixDisable:skl */ > > + WA_SET_BIT_MASKED(HDC_CHICKEN0, > > + HDC_FENCE_DEST_SLM_DISABLE | > > + HDC_BARRIER_PERFORMANCE_DISABLE); > > + > > return 0; > > } > > > > -- > > 2.4.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
