During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@xxxxxxxxx>
Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 895d7c7..cab2ac8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2171,6 +2171,9 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
static void intel_disable_pipe(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dsi *intel_dsi;
+ struct drm_device *dev = crtc->base.dev;
enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
enum pipe pipe = crtc->pipe;
int reg;
@@ -2189,6 +2192,16 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
if ((val & PIPECONF_ENABLE) == 0)
return;
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ if (encoder->type == INTEL_OUTPUT_DSI) {
+ intel_dsi = enc_to_intel_dsi(&encoder->base);
+ if (intel_dsi && (intel_dsi->operation_mode ==
+ INTEL_DSI_COMMAND_MODE))
+ val = val & ~PIPECONF_MIPI_DSR_ENABLE;
+ break;
+ }
+ }
+
/*
* Double wide has implications for planes
* so best keep it disabled when not needed.
--
1.7.9.5
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