On Tue, May 26, 2015 at 08:27:23PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The primary plane frobbing was removed from the sprite code in
> commit ecce87ea3ab55ad0dc64460e6422c357d158a55e
> Author: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Date: Tue Apr 21 17:12:50 2015 +0300
>
> drm/i915: Remove implicitly disabling primary plane for now
>
> but the intel_flush_primary_plane() calls were left behind. Replace them
> with straight forward POSTING_READ() of the sprite surface address
> register.
>
> The other user of intel_flush_primary_plane() is g4x_disable_trickle_feed()
> where we can just inline the steps directly.
>
> This allows intel_flush_primary_plane() to be killed off.
>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 14 --------------
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> drivers/gpu/drm/i915/intel_sprite.c | 30 +++++++-----------------------
> 4 files changed, 11 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 657a333..27792c1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2210,20 +2210,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
> intel_wait_for_pipe_off(crtc);
> }
>
> -/*
> - * Plane regs are double buffered, going from enabled->disabled needs a
> - * trigger in order to latch. The display address reg provides this.
> - */
> -void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
> - enum plane plane)
> -{
> - struct drm_device *dev = dev_priv->dev;
> - u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
> -
> - I915_WRITE(reg, I915_READ(reg));
> - POSTING_READ(reg);
> -}
> -
> /**
> * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
> * @plane: plane to be enabled
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 02d8317..2afb31a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1383,8 +1383,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
>
> /* intel_sprite.c */
> int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
> -void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
> - enum plane plane);
> int intel_plane_restore(struct drm_plane *plane);
> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 48bb7ec..db78998 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5876,13 +5876,15 @@ static void ibx_init_clock_gating(struct drm_device *dev)
> static void g4x_disable_trickle_feed(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - int pipe;
> + enum pipe pipe;
>
> for_each_pipe(dev_priv, pipe) {
> I915_WRITE(DSPCNTR(pipe),
> I915_READ(DSPCNTR(pipe)) |
> DISPPLANE_TRICKLE_FEED_DISABLE);
> - intel_flush_primary_plane(dev_priv, pipe);
> +
> + I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
> + POSTING_READ(DSPSURF(pipe));
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 2a90308..8193a35 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -282,7 +282,6 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
>
> I915_WRITE(PLANE_CTL(pipe, plane), 0);
>
> - /* Activate double buffered register update */
> I915_WRITE(PLANE_SURF(pipe, plane), 0);
> POSTING_READ(PLANE_SURF(pipe, plane));
>
> @@ -339,7 +338,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> struct drm_device *dev = dplane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(dplane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int pipe = intel_plane->pipe;
> int plane = intel_plane->plane;
> @@ -453,8 +451,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> I915_WRITE(SPCNTR(pipe, plane), sprctl);
> I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
> sprsurf_offset);
> -
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + POSTING_READ(SPSURF(pipe, plane));
> }
>
> static void
> @@ -463,21 +460,17 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
> struct drm_device *dev = dplane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(dplane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_plane->pipe;
> int plane = intel_plane->plane;
>
> I915_WRITE(SPCNTR(pipe, plane), 0);
>
> - /* Activate double buffered register update */
> I915_WRITE(SPSURF(pipe, plane), 0);
> -
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + POSTING_READ(SPSURF(pipe, plane));
>
> intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
> }
>
> -
> static void
> ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> struct drm_framebuffer *fb,
> @@ -489,7 +482,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> struct drm_device *dev = plane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> enum pipe pipe = intel_plane->pipe;
> u32 sprctl, sprscale = 0;
> @@ -599,8 +591,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> I915_WRITE(SPRCTL(pipe), sprctl);
> I915_WRITE(SPRSURF(pipe),
> i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
> -
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + POSTING_READ(SPRSURF(pipe));
> }
>
> static void
> @@ -609,17 +600,15 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
> struct drm_device *dev = plane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_plane->pipe;
>
> I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
> /* Can't leave the scaler enabled... */
> if (intel_plane->can_scale)
> I915_WRITE(SPRSCALE(pipe), 0);
> - /* Activate double buffered register update */
> - I915_WRITE(SPRSURF(pipe), 0);
>
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + I915_WRITE(SPRSURF(pipe), 0);
> + POSTING_READ(SPRSURF(pipe));
> }
>
> static void
> @@ -633,7 +622,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> struct drm_device *dev = plane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int pipe = intel_plane->pipe;
> unsigned long dvssurf_offset, linear_offset;
> @@ -730,8 +718,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> I915_WRITE(DVSCNTR(pipe), dvscntr);
> I915_WRITE(DVSSURF(pipe),
> i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
> -
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + POSTING_READ(DVSSURF(pipe));
> }
>
> static void
> @@ -740,17 +727,14 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
> struct drm_device *dev = plane->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> int pipe = intel_plane->pipe;
>
> I915_WRITE(DVSCNTR(pipe), 0);
> /* Disable the scaler */
> I915_WRITE(DVSSCALE(pipe), 0);
>
> - /* Flush double buffered register updates */
> I915_WRITE(DVSSURF(pipe), 0);
> -
> - intel_flush_primary_plane(dev_priv, intel_crtc->plane);
> + POSTING_READ(DVSSURF(pipe));
> }
>
> static int
> --
> 2.3.6
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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