The line between maxfifo and SR is a blurry one. Since we treat them as the same thing, just read out the registers set up in intel_set_memory_cxsr(). References: https://bugs.freedesktop.org/show_bug.cgi?id=89792 Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx> --- On 04/02/2015 11:42 AM, Ville Syrjälä wrote: > On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote: >> I guess this is a lie for 8xx, but newer stuff takes care of this for >> us. >> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792 >> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> >> --- >> drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >> b/drivers/gpu/drm/i915/i915_debugfs.c >> index 91c945b..a8f42a7 100644 >> --- a/drivers/gpu/drm/i915/i915_debugfs.c >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> @@ -1686,6 +1686,8 @@ static int i915_sr_status(struct seq_file *m, >> void *unused) >> sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; >> else if (IS_PINEVIEW(dev)) >> sr_enabled = I915_READ(DSPFW3) & >> PINEVIEW_SELF_REFRESH_EN; >> + else >> + sr_enabled = true; /* other platforms don't need >> enabling */ > > Not true actually. > > The line between maxfifo and SR is a blurry one. We treat them as the > same thing. So I think this should just read out whatever registers > we set up in intel_set_memory_cxsr(). Ville, does this patch does what you meant with the above sentence. I'm clueless about self-refresh, so I just paraphrased you in the commit message. Ander --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index fece922..d80de9d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1731,6 +1731,8 @@ static int i915_sr_status(struct seq_file *m, void *unused) sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; else if (IS_PINEVIEW(dev)) sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + else if (IS_VALLEYVIEW(dev)) + sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; intel_runtime_pm_put(dev_priv); -- 2.1.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
