On Mon, May 18, 2015 at 8:46 AM, Imre Deak <imre.deak@xxxxxxxxx> wrote:
> The divider value to convert from CZ clock rate to ms needs a +1
> adjustment on VLV just like on CHV.
On CHV this was an special case for 320MHz, on VLV we have only one
freq possible or it is global?
The spec I have here doesn't show different freqs here on VLV as we have on CHV.
> This matches both the spec and
Anyway, even on CHV I couldn't find where spec mentions this. Could
you please point me or share your spec in pvt so I can give a rv-b
here.
> the accuracy test by pm_rc6_residency.
>
> Testcase: igt/pm_rc6_residency
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_sysfs.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 2476268..aa99efc 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -76,6 +76,8 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
> /* chv counts are one less */
> czcount_30ns += 1;
> }
> + } else {
> + czcount_30ns += 1;
> }
>
> if (units == 0)
> --
> 2.1.4
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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