At the moment, even if we fail to find a suitable divider, we'll still
try to set the mode with bogus parameters.
Just fail the modeset if we can't generate the frequency.
Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ff5eb05..12592bf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1111,7 +1111,7 @@ struct skl_wrpll_params {
uint32_t central_freq;
};
-static void
+static bool
skl_ddi_calculate_wrpll(int clock /* in Hz */,
struct skl_wrpll_params *wrpll_params)
{
@@ -1192,6 +1192,7 @@ found:
if (min_dco_index > 2) {
WARN(1, "No valid parameters found for pixel clock: %dHz\n",
clock);
+ return false;
} else {
wrpll_params->central_freq = dco_central_freq[min_dco_index];
@@ -1258,6 +1259,8 @@ found:
wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
}
+
+ return true;
}
@@ -1282,7 +1285,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
- skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
+ if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
+ return false;
cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
--
2.1.0
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