On Wed, May 06, 2015 at 02:04:50PM +0100, Damien Lespiau wrote:
> Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
>
> The problem was introduced in the original patch:
>
> commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
> Author: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Date: Mon Feb 9 19:33:20 2015 +0000
>
> drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
>
> Reported-by: Robert Beckett <robert.beckett@xxxxxxxxx>
> Cc: Robert Beckett <robert.beckett@xxxxxxxxx>
> Cc: Nick Hoath <nicholas.hoath@xxxxxxxxx>
>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
FYI the code in skl_init_clock_gating() is also wrong since this is
a masked register.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5436ab0..6a1875a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5718,7 +5718,7 @@ enum skl_disp_power_wells {
> #define HSW_NDE_RSTWRN_OPT 0x46408
> #define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
>
> -#define FF_SLICE_CS_CHICKEN2 0x02e4
> +#define FF_SLICE_CS_CHICKEN2 0x20e4
> #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
>
> /* GEN7 chicken */
> --
> 2.1.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
