On 05/05/2015 11:57 AM, Peter Hurley wrote: > On 05/05/2015 11:42 AM, Daniel Vetter wrote: >> I'm also somewhat confused about how you to a line across both cpus for >> barriers because barriers only have cpu-local effects (which is why we >> always need a barrier on both ends of a transaction). I'm sorry if my barrier notation confuses you; I find that it clearly identifies matching pairs. Also, there is a distinction between "can be visible" and "must be visible"; the load and stores themselves are not cpu-local. Regards, Peter Hurley _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
