On Mon, May 04, 2015 at 04:21:20PM +0200, Daniel Vetter wrote:
> On Mon, May 04, 2015 at 04:14:41PM +0200, Daniel Vetter wrote:
> > On Thu, Apr 23, 2015 at 12:54:37PM +0100, Chris Wilson wrote:
> > > Since
> > >
> > > commit 43566dedde54f9729113f5f9fde77d53e75e61e9
> > > Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > > Date: Fri Jan 2 16:29:29 2015 +0530
> > >
> > > drm/i915: Broaden application of set-domain(GTT)
> > >
> > > we allowed objects to be in the GTT domain, but unbound. Therefore
> > > removing the GTT cache domain when removing the GGTT vma is no longer
> > > semantically correct.
> > >
> > > An unfortunate side-effect is we lose the wondrously named
> > > i915_gem_object_finish_gtt(), not to be confused with
> > > i915_gem_gtt_finish_object()!
> >
> > What are we going to do without that bit of hilarity ...
> > >
> > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > > Cc: Akash Goel <akash.goel@xxxxxxxxx>
> > > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> >
> > Queued for -next (with the rebase conflict resolved because I don't have
> > your tree), thanks for the patch.
>
> Well not since there's another finish_gtt in my tree in set_cache_level.
> And tbh I'm not sure what to do with that one, but it seems rather
> redundnant. Care to respin/rebase?
There's a patch on list to remove it, I think I am about 90% of the way
through convincing Tvrtko that that patch is golden.
Between Akash any myself we have a had a little debate over whether we
want to keep the mb() here or not. The consensus, at least how I have the
patch in my tree, is to use:
if (vma->map_and_fenceable) {
ret = i915_gem_object_put_fence(obj);
if (ret)
return ret;
/* Force a pagefault for domain tracking on next user access */
i915_gem_release_mmap(obj);
/* Wait for any direct GTT access to complete */
if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
mb();
}
as the replacement. The worry is that we don't have sufficient barriers
between the user doing their GTT writes through one BAR and updating the
PTE through another.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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