This patch is adding NV12 support to skylake sprite plane programming. It is covering linear/X/Y/Yf tiling formats for 0 and 180 rotations. For 90/270 rotation, Y and UV subplanes should be treated as separate surfaces and GTT remapping for rotation should be done separately for each subplane. Once GEM adds support for seperate remappings for two subplanes, 90/270 support to be added to plane programming. Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx> Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_sprite.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index aa2998f..2a03905 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -201,6 +201,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int x_offset, y_offset; struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; int scaler_id; + u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; + u32 tile_row_adjustment = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -247,24 +249,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, plane_size = (src_w << 16) | src_h; x_offset = stride * tile_height - y - (src_h + 1); y_offset = x; + + /* + * TBD: For NV12 90/270 rotation, Y and UV subplanes should + * be treated as separate surfaces and GTT remapping for + * rotation should be done separately for each subplane. + * Enable support once seperate remappings are available. + */ } else { stride = fb->pitches[0] / stride_div; plane_size = (src_h << 16) | src_w; x_offset = x; y_offset = y; + tile_height = PAGE_SIZE / stride_div; + + if (fb->pixel_format == DRM_FORMAT_NV12) { + int height_in_mem = (fb->offsets[1]/fb->pitches[0]); + /* + * If UV starts from middle of a page, then UV start should + * be programmed to beginning of that page. And offset into that + * page to be programmed into y-offset + */ + tile_row_adjustment = height_in_mem % tile_height; + aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment); + aux_x_offset = DIV_ROUND_UP(x, 2); + aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment; + /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ + aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? + stride / 2 : stride; + } } plane_offset = y_offset << 16 | x_offset; I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); I915_WRITE(PLANE_STRIDE(pipe, plane), stride); I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); + I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride); + I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 | aux_x_offset); /* program plane scaler */ if (scaler_id >= 0) { uint32_t ps_ctrl = 0; - DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, - PS_PLANE_SEL(plane)); ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | crtc_state->scaler_state.scalers[scaler_id].mode; I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); @@ -275,6 +301,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), 0); } else { + WARN_ON(fb->pixel_format == DRM_FORMAT_NV12); I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); } -- 1.7.9.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx