On 30/04/15 15:33, Michel Thierry wrote: > On 4/30/2015 3:22 PM, Ville Syrjälä wrote: >> On Thu, Apr 30, 2015 at 02:59:34PM +0100, Michel Thierry wrote: >>> The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: "drm/i915/gen8: >>> page directories rework allocation" added an overflow warning, but the >>> mask had an extra 0. Use typo-prone option suggested by Dave instead. >>> >>> This check will be unnecessary after gen8_alloc_va_range handles more >>> than 4 PDPs (48b addressing). >>> >>> Reported-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx> >>> Cc: Dave Gordon <david.s.gordon@xxxxxxxxx> >>> Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> >>> --- >>> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++-- >>> 1 file changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c >>> b/drivers/gpu/drm/i915/i915_gem_gtt.c >>> index 6fae6bd..6d894fc 100644 >>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c >>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c >>> @@ -756,8 +756,8 @@ static int >>> gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, >>> >>> WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); >>> >>> - /* FIXME: PPGTT container_of won't work for 64b */ >>> - WARN_ON((start + length) > 0x800000000ULL); >>> + /* FIXME: upper bound must not overflow 31 bits */ >>> + WARN_ON((start + length) & (~0ULL << 31)); >> >> Why is it 31 and not 32? > > Right, the check really should be (start + length) >= 0x100000000ULL. Something with '32' in it might be more obvious and save anyone having to count the zeroes ... and a comment that also mentioned the limit: /* FIXME: for now, upper bound must fit in 32 bits */ WARN_ON((start + length) >= (1ULL << 32)) WARN_ON((start + length) & (~0ULL << 32)) WARN_ON((start + length) >> 32) != 0) .Dave. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
