On Monday 13 April 2015 05:40 PM, Ville Syrjälä wrote:
On Mon, Apr 13, 2015 at 02:55:12PM +0300, Jani Nikula wrote:
On Thu, 05 Mar 2015, deepak.s@xxxxxxxxxxxxxxx wrote:
From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
When GPU is idle on VLV, Request freq to punit should be good enough to
get the voltage back to VNN. Also, make sure gfx clock force applies
before requesting the freq fot vlv.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
suggested-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
Deepak, these patches seem to have fallen through the cracks. Are they
still valid? Please rebase and repost if they are.
Ville, your opinion also appreciated.
I don't I have any VLVs old enough to hit this, so can't really confirm
one way or the other.
Hi Jesse, Can you please review the patch?
Thanks
Deepak
BR,
Jani.
---
drivers/gpu/drm/i915/intel_pm.c | 20 ++++----------------
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e710b43..2e1ed07 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3894,7 +3894,7 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
* * If Gfx is Idle, then
* 1. Mask Turbo interrupts
* 2. Bring up Gfx clock
- * 3. Change the freq to Rpn and wait till P-Unit updates freq
+ * 3. Request the freq to Rpn.
* 4. Clear the Force GFX CLK ON bit so that Gfx can down
* 5. Unmask Turbo interrupts
*/
@@ -3902,8 +3902,8 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
- /* CHV and latest VLV don't need to force the gfx clock */
- if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
+ /* CHV don't need to force the gfx clock */
+ if (IS_CHERRYVIEW(dev)) {
Why was the stepping check removed?
valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
return;
}
@@ -3920,20 +3920,8 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
gen6_sanitize_rps_pm_mask(dev_priv, ~0));
vlv_force_gfx_clock(dev_priv, true);
-
- dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
-
- vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
- dev_priv->rps.min_freq_softlimit);
-
- if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
- & GENFREQSTATUS) == 0, 100))
- DRM_ERROR("timed out waiting for Punit\n");
-
+ valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
vlv_force_gfx_clock(dev_priv, false);
-
- I915_WRITE(GEN6_PMINTRMSK,
- gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
}
void gen6_rps_idle(struct drm_i915_private *dev_priv)
--
1.9.1
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--
Jani Nikula, Intel Open Source Technology Center
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