On Wed, 2015-04-15 at 17:15 +0300, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx>
>
> PORT_CLK_SEL programming is needed only on HSW/BDW.
>
> v2:
> - don't program PORT_CLK_SEL from mst encoders either (imre)
> v3:
> - fix the check for GEN9+ in intel_mst_pre_enable_dp() (damien)
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
Reviewed-by: Sagar Kamble <sagar.a.kamble at intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 31cadb8..6bdccb2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1565,7 +1565,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>
> I915_WRITE(DPLL_CTRL2, val);
>
> - } else {
> + } else if (INTEL_INFO(dev)->gen < 9) {
> WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
> I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
> }
> @@ -1624,7 +1624,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
> if (IS_SKYLAKE(dev))
> I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> DPLL_CTRL2_DDI_CLK_OFF(port)));
> - else
> + else if (INTEL_INFO(dev)->gen < 9)
> I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 7335089..3945057 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
> if (intel_dp->active_mst_links == 0) {
> enum port port = intel_ddi_get_encoder_port(encoder);
>
> - I915_WRITE(PORT_CLK_SEL(port),
> - intel_crtc->config->ddi_pll_sel);
> + /* FIXME: add support for SKL */
> + if (INTEL_INFO(dev)->gen < 9)
> + I915_WRITE(PORT_CLK_SEL(port),
> + intel_crtc->config->ddi_pll_sel);
>
> intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
>
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