On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepak.s@xxxxxxxxxxxxxxx wrote:
> From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..a642a58 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
> #define GTFIFOCTL 0x120008
> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>
> #define HSW_IDICR 0x9008
> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4dd8b41..2b86915 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
> /* WaDisableSDEUnitClockGating:chv */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> + /* WaDisableShadowRegForCpd */
> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
> + GT_FIFO_CTL_RC6_POLICY_STALL);
uncore early sanitize would still seem like the better place for this.
> }
>
> static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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