On Tue, Apr 07, 2015 at 04:21:14PM +0100, Chris Wilson wrote:
> We are conservative on the amount of free space available in the ring to
> avoid overruning the potential MI_INTERRUPT after the seqno write.
> Further undermining the justification for the change was that it was
> applied incorrectly.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Hm, where are we conservative with our estimates? Could we just wait for
req->head instead? And I don't see what's been implemented wrongly with
postfix.
Looking at
commit a71d8d94525e8fd855c0466fb586ae1cb008f3a2
Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Date: Wed Feb 15 11:25:36 2012 +0000
drm/i915: Record the tail at each request and use it to estimate the head
->postfix does get updated where ->tail was, Nick just renamed it from
->tail to ->postfix since execlist used ->tail with a different meaning.
Or do I miss something?
> diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
> index 9a27ec7100ef..f45caa6af7d2 100644
> --- a/drivers/gpu/drm/i915/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/intel_dvo.c
> @@ -496,7 +496,7 @@ void intel_dvo_init(struct drm_device *dev)
> int gpio;
> bool dvoinit;
> enum pipe pipe;
> - uint32_t dpll[2];
> + uint32_t dpll[I915_MAX_PIPES];
Unrelated change and there's indeed only 2 dvo plls ever on gen2.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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