On Fri, Apr 03, 2015 at 10:43:29AM +0100, Chris Wilson wrote:
> On Thu, Nov 20, 2014 at 09:26:30AM +0100, Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > index 749ab485569e..03c675a4476e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > @@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> > }
> > break;
> > }
> > +
> > + /* check for L-shaped memory aka modified enhanced addressing */
> > + if (IS_GEN4(dev)) {
> > + uint32_t ddc2 = I915_READ(DCC2);
> > +
> > + if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
> > + dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
> > + }
> > +
> > if (dcc == 0xffffffff) {
> > DRM_ERROR("Couldn't read from MCHBAR. "
> > "Disabling tiling.\n");
>
> I resurrected my dual-channel evenly loaded gm45 and to my surprise
> found it reporting a L-shaped memory layout.
Well my gm45 is also dual-channel and evenly loaded and still mangles
tiled buffers when going through swap. Is gem_tiled_swapping happy on your
box?
> Perhaps the if ((ddc2 & DISABLE) == 0) is inverted or is not the truly
> magic bit?
It was the best one I could find - given how old this all is now I think
some false positives are acceptable in the test. I did try a few other
things which did all fail.
-Daniel
> ickle@x200s $ sudo cat /sys/kernel/debug/dri/0/i915_swizzle_info
> bit6 swizzle for X-tiling = bit9/bit10/bit11
> bit6 swizzle for Y-tiling = bit9/bit11
> DDC = 0x000f0002
> DDC2 = 0x00000010
> C0DRB3 = 0x0000
> C1DRB3 = 0x0000
> L-shaped memory detected
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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