On Wed, 2015-04-01 at 14:22 -0700, Jesse Barnes wrote: > Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this > reg. If it's unlocked, we can just restore the previous value, and if > it's locked (in case the BIOS re-programmed it for us) the write will be > ignored and we'll still have "did it move" sanity check in the PM code to > warn us if something is still amiss. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=89611 > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Yea, the BIOS is supposed to program this reg according to the Gunit doc, but we can't have any guarantee anyway.. I guess this is a problem only for S3, but I can't see any problem saving/restoring it also during s0ix, so: Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index c1a3cdb5..4d6d6f0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) > /* Gunit-Display CZ domain, 0x182028-0x1821CF */ > s->gu_ctl0 = I915_READ(VLV_GU_CTL0); > s->gu_ctl1 = I915_READ(VLV_GU_CTL1); > + s->pcbr = I915_READ(VLV_PCBR); > s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); > > /* > @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) > /* Gunit-Display CZ domain, 0x182028-0x1821CF */ > I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); > I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); > + I915_WRITE(VLV_PCBR, s->pcbr); > I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); > } > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index b13c552..f3ac683 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -994,6 +994,7 @@ struct vlv_s0ix_state { > /* Display 2 CZ domain */ > u32 gu_ctl0; > u32 gu_ctl1; > + u32 pcbr; > u32 clock_gate_dis2; > }; > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
