Decode the register for BXT too and don't decode rotation and bpc on platforms where these fields are not defined. Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> --- tools/intel_reg_dumper.c | 82 +++++++++++++++++++++++++++++------------------- 1 file changed, 49 insertions(+), 33 deletions(-) diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index d539f96..f03ab35 100644 --- a/tools/intel_reg_dumper.c +++ b/tools/intel_reg_dumper.c @@ -155,10 +155,17 @@ DEBUGSTRING(i830_debug_pipeconf) bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide"; - if (HAS_PCH_SPLIT(devid)) { + if (HAS_PCH_SPLIT(devid) || IS_BROXTON(devid)) { const char *bpc, *rotation; + int interlace_mode; - switch ((val >> 21) & 7) { + if ((IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || + IS_BROADWELL(devid) || IS_GEN9(devid))) + interlace_mode = (val >> 21) & 3; + else + interlace_mode = (val >> 21) & 7; + + switch (interlace_mode) { case 0: interlace = "pf-pd"; break; @@ -179,40 +186,49 @@ DEBUGSTRING(i830_debug_pipeconf) break; } - switch ((val >> 14) & 3) { - case 0: - rotation = "rotate 0"; - break; - case 1: - rotation = "rotate 90"; - break; - case 2: - rotation = "rotate 180"; - break; - case 3: - rotation = "rotate 270"; - break; + rotation = ""; + if (IS_HASWELL(devid) || IS_IVYBRIDGE(devid) || + IS_GEN6(devid) || IS_GEN5(devid)) { + switch ((val >> 14) & 3) { + case 0: + rotation = "rotate 0"; + break; + case 1: + rotation = "rotate 90"; + break; + case 2: + rotation = "rotate 180"; + break; + case 3: + rotation = "rotate 270"; + break; + } } - switch (val & (7 << 5)) { - case PIPECONF_8BPP: - bpc = "8bpc"; - break; - case PIPECONF_10BPP: - bpc = "10bpc"; - break; - case PIPECONF_6BPP: - bpc = "6bpc"; - break; - case PIPECONF_12BPP: - bpc = "12bpc"; - break; - default: - bpc = "invalid bpc"; - break; + bpc = ""; + if (IS_IVYBRIDGE(devid) || IS_GEN6(devid) || IS_GEN5(devid)) { + switch (val & (7 << 5)) { + case PIPECONF_8BPP: + bpc = "8bpc"; + break; + case PIPECONF_10BPP: + bpc = "10bpc"; + break; + case PIPECONF_6BPP: + bpc = "6bpc"; + break; + case PIPECONF_12BPP: + bpc = "12bpc"; + break; + default: + bpc = "invalid bpc"; + break; + } } - snprintf(result, len, "%s, %s, %s, %s, %s", enabled, bit30, - interlace, rotation, bpc); + snprintf(result, len, "%s, %s, %s, %s%s%s", enabled, bit30, + interlace, + rotation, rotation[0] ? ", " : "", + bpc); } else if (IS_GEN4(devid)) { switch ((val >> 21) & 7) { case 0: -- 2.1.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx