On 3/24/2015 12:54 PM, Mika Kuoppala wrote:
The faulting virtual address is >32bits and has been moved to different registers. Add to error state and output upper register first, in the same line for easy reconstruction of the fault address. v2: correct gen masking (Michel) v3: s/TBL/TLB (Ville) Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 3 files changed, 15 insertions(+)
Thanks for noticing that last typo... Reviewed-by: Michel Thierry <michel.thierry@xxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
