On 03/17/2015 02:40 AM, Imre Deak wrote: > From: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx> > > Assign PLL for pipe (dependent on port attached to the pipe) > > v2: > - fix incorrect encoder vs. new_encoder check for crtc (imre) > > v3: > - warn and return error if no encoder is attached (imre) > > Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx> (v2) > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ddi.c | 21 ------------------ > drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > 3 files changed, 42 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index fa4f8f4..0a5d71e 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -491,27 +491,6 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) > return ret; > } > > -static struct intel_encoder * > -intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc) > -{ > - struct drm_device *dev = crtc->base.dev; > - struct intel_encoder *intel_encoder, *ret = NULL; > - int num_encoders = 0; > - > - for_each_intel_encoder(dev, intel_encoder) { > - if (intel_encoder->new_crtc == crtc) { > - ret = intel_encoder; > - num_encoders++; > - } > - } > - > - WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, > - pipe_name(crtc->pipe)); > - > - BUG_ON(ret == NULL); > - return ret; > -} > - > #define LC_FREQ 2700 > #define LC_FREQ_2K U64_C(LC_FREQ * 2000) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3606366..411bf50 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4037,6 +4037,27 @@ void intel_put_shared_dpll(struct intel_crtc *crtc) > crtc->config->shared_dpll = DPLL_ID_PRIVATE; > } > > +struct intel_encoder * > +intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc) > +{ > + struct drm_device *dev = crtc->base.dev; > + struct intel_encoder *intel_encoder, *ret = NULL; > + int num_encoders = 0; > + > + for_each_intel_encoder(dev, intel_encoder) { > + if (intel_encoder->new_crtc == crtc) { > + ret = intel_encoder; > + num_encoders++; > + } > + } > + > + WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, > + pipe_name(crtc->pipe)); > + > + BUG_ON(ret == NULL); > + return ret; > +} > + > struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, > struct intel_crtc_state *crtc_state) > { > @@ -4057,6 +4078,26 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, > goto found; > } > > + if (IS_BROXTON(dev_priv->dev)) { > + /* PLL is attached to port in bxt */ > + struct intel_encoder *encoder; > + struct intel_digital_port *intel_dig_port; > + > + encoder = intel_ddi_get_crtc_new_encoder(crtc); > + if (WARN_ON(!encoder)) > + return NULL; > + > + intel_dig_port = enc_to_dig_port(&encoder->base); > + /* 1:1 mapping between ports and PLLs */ > + i = (enum intel_dpll_id)intel_dig_port->port; > + pll = &dev_priv->shared_dplls[i]; > + DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", > + crtc->base.base.id, pll->name); > + WARN_ON(pll->new_config->crtc_mask); > + > + goto found; > + } > + > for (i = 0; i < dev_priv->num_shared_dpll; i++) { > pll = &dev_priv->shared_dplls[i]; > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 56a5cc9..097fb85 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -991,6 +991,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, > bool state); > #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) > #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) > +struct intel_encoder *intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc); > struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, > struct intel_crtc_state *state); > void intel_put_shared_dpll(struct intel_crtc *crtc); > Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx