On ti, 2015-03-17 at 11:48 +0100, Daniel Vetter wrote:
> On Tue, Mar 17, 2015 at 11:39:50AM +0200, Imre Deak wrote:
> > From: Shashank Sharma <shashank.sharma@xxxxxxxxx>
> >
> > In BXT, DDI hotplug control has been moved to CPU from PCH.
> > This patch adds a new IRQ setup function for BXT which:
> > 1. Checks which HPD ports are requested to be enabled by encoders.
> > 2. Enables those ports in the hot plug control register.
> > 3. Un-masks these port interrupts in the IMR register.
> > 4. Enables these port interrupts in the IER register.
> >
> > V3: Kept the default HPD filter count to default (500 us) as per
> > satheesh's comment
> > v4: Remove unused HPD filter defines (Damien)
> > v5: warn if trying to setup HPD on port A (imre)
> >
> > Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx>
> > Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> > Signed-off-by: Shashank Sharma <shashank.sharma@xxxxxxxxx> (v4)
> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++
> > 2 files changed, 73 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 49ad5fb..a51c00e 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -88,6 +88,12 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { /* i915 and valleyview are th
> > [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
> > };
> >
> > +/* BXT hpd list */
> > +static const u32 hpd_bxt[] = {
> > + [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
> > + [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
> > +};
> > +
> > /* IIR can theoretically queue up two events. Be paranoid. */
> > #define GEN8_IRQ_RESET_NDX(type, which) do { \
> > I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
> > @@ -3235,6 +3241,44 @@ static void ibx_hpd_irq_setup(struct drm_device *dev)
> > I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
> > }
> >
> > +static void bxt_hpd_irq_setup(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct drm_mode_config *mode_config = &dev->mode_config;
> > + struct intel_encoder *intel_encoder;
> > + u32 hotplug_port = 0;
> > + u32 hotplug_ctrl;
> > +
> > + /* Now, enable HPD */
> > + list_for_each_entry(intel_encoder, &mode_config->encoder_list,
> > + base.head) {
> > + if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
> > + == HPD_ENABLED)
> > + hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
> > + }
> > +
> > + /* Mask all HPD control bits */
> > + hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
> > +
> > + /* Enable requested port in hotplug control */
> > + /* TODO: implement (short) HPD support on port A */
> > + WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
> > + if (hotplug_port & BXT_DE_PORT_HP_DDIB)
> > + hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
> > + if (hotplug_port & BXT_DE_PORT_HP_DDIC)
> > + hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
> > + I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
> > +
> > + /* Unmask DDI hotplug in IMR */
> > + hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
> > + I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
> > +
> > + /* Enable DDI hotplug in IER */
> > + hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
> > + I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
> > + POSTING_READ(GEN8_DE_PORT_IER);
>
> Out of paranoi I checked the locking here, but we seem to be save already
> with dev_priv->irq_lock.
>
> > +}
> > +
> > static void ibx_irq_postinstall(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4355,7 +4399,10 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > dev->driver->irq_uninstall = gen8_irq_uninstall;
> > dev->driver->enable_vblank = gen8_enable_vblank;
> > dev->driver->disable_vblank = gen8_disable_vblank;
> > - dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> > + if (HAS_PCH_SPLIT(dev))
> > + dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
> > + else
> > + dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> > } else if (HAS_PCH_SPLIT(dev)) {
> > dev->driver->irq_handler = ironlake_irq_handler;
> > dev->driver->irq_preinstall = ironlake_irq_reset;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 60ff760..1efee7d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5247,6 +5247,14 @@ enum skl_disp_power_wells {
> > #define GEN9_AUX_CHANNEL_B (1 << 25)
> > #define GEN8_AUX_CHANNEL_A (1 << 0)
> >
> > +/* Gen 9 BXT DDI Hotplug */
> > +#define BXT_DE_PORT_HP_DDIC (1 << 5)
> > +#define BXT_DE_PORT_HP_DDIB (1 << 4)
> > +#define BXT_DE_PORT_HP_DDIA (1 << 3)
> > +#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
> > + BXT_DE_PORT_HP_DDIB | \
> > + BXT_DE_PORT_HP_DDIC)
>
> Generally we interleave definitions for different platforms if it's the
> same register.
The list was already a bit mis-ordered, but agreed, will clean this up.
> > +
> > #define GEN8_DE_MISC_ISR 0x44460
> > #define GEN8_DE_MISC_IMR 0x44464
> > #define GEN8_DE_MISC_IIR 0x44468
> > @@ -5258,6 +5266,23 @@ enum skl_disp_power_wells {
> > #define GEN8_PCU_IIR 0x444e8
> > #define GEN8_PCU_IER 0x444ec
> >
> > +/* BXT hotplug control */
> > +#define BXT_HOTPLUG_CTL 0xC4030
> > +#define BXT_DDIA_HPD_ENABLE (1 << 28)
> > +#define BXT_DDIB_HPD_ENABLE (1 << 4)
> > +#define BXT_DDIC_HPD_ENABLE (1 << 12)
> > +#define BXT_HOTPLUG_CTL_MASK (BXT_DDIA_HPD_ENABLE | \
> > + BXT_DDIB_HPD_ENABLE | \
> > + BXT_DDIC_HPD_ENABLE)
> > +
> > +/* Hot plug status */
> > +#define BXT_DDIA_HPD_STATUS (3 << 24)
> > +#define BXT_DDIB_HPD_STATUS (3 << 0)
> > +#define BXT_DDIC_HPD_STATUS (3 << 8)
> > +#define BXT_HPD_STATUS_MASK (BXT_DDIA_HPD_STATUS | \
> > + BXT_DDIB_HPD_STATUS | \
> > + BXT_DDIC_HPD_STATUS)
> > +
> > #define ILK_DISPLAY_CHICKEN2 0x42004
> > /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> > #define ILK_ELPIN_409_SELECT (1 << 25)
> > --
> > 2.1.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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