Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics.
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
Documentation/DocBook/drm.tmpl | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 10 +++++++---
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7a45775..327757f 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -4067,7 +4067,7 @@ int num_ioctls;</synopsis>
<title>DPIO</title>
!Pdrivers/gpu/drm/i915/i915_reg.h DPIO
<table id="dpiox2">
- <title>Dual channel PHY (VLV/CHV)</title>
+ <title>Dual channel PHY (VLV/CHV/BXT)</title>
<tgroup cols="8">
<colspec colname="c0" />
<colspec colname="c1" />
@@ -4118,7 +4118,7 @@ int num_ioctls;</synopsis>
</tgroup>
</table>
<table id="dpiox1">
- <title>Single channel PHY (CHV)</title>
+ <title>Single channel PHY (CHV/BXT)</title>
<tgroup cols="4">
<colspec colname="c0" />
<colspec colname="c1" />
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a3579c0..95532b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -718,7 +718,7 @@ enum skl_disp_power_wells {
/**
* DOC: DPIO
*
- * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
+ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
* ports. DPIO is the name given to such a display PHY. These PHYs
* don't follow the standard programming model using direct MMIO
* registers, and instead their registers must be accessed trough IOSF
@@ -773,9 +773,13 @@ enum skl_disp_power_wells {
*
* Note: digital port B is DDI0, digital port C is DDI1,
* digital port D is DDI2
+ *
+ * On BXT the above mappings apply for both the dual and single channel PHY,
+ * with the difference that any of the three ports can connect to any of the
+ * three pipes. Also the single channel PHY is used for port A (DDI2/EDP).
*/
/*
- * Dual channel PHY (VLV/CHV)
+ * Dual channel PHY (VLV/CHV/BXT)
* ---------------------------------
* | CH0 | CH1 |
* | CMN/PLL/REF | CMN/PLL/REF |
@@ -787,7 +791,7 @@ enum skl_disp_power_wells {
* | DDI0 | DDI1 | DP/HDMI ports
* ---------------------------------
*
- * Single channel PHY (CHV)
+ * Single channel PHY (CHV/BXT)
* -----------------
* | CH0 |
* | CMN/PLL/REF |
--
2.1.0
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