On Tue, Mar 10, 2015 at 01:15:27PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> When enabling planes during .crtc_enable() we currently want to update
> the watermarks before enabling the planes. We already do it once just
> before enabling the pipe, but at that point out derived plane state is
> still out of whack, so we need to do it again after the .atomic_check()
> hooks have been called.
>
> What this means is now we could actually start to trust the derived
> plane state (clipped size, 'visible', etc.) in the watermark code.
>
> The pre pipe enable watermark update is supposed to be just make sure
> the other pipes are ready to have their FIFOs potentially reduced, so we
> need to keep it there as well.
>
> Since we don't yet have proper two-part watermark update leave the
> watermakrs alone in the plane disable case. This way they'll get updated
> only after the planes and pipe have all been turned off.
>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 33680a8..a9201a7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4167,6 +4167,8 @@ static void _intel_crtc_enable_planes(struct intel_crtc *crtc)
> state->visible = false;
> }
>
> + intel_update_watermarks(&crtc->base);
> +
> crtc_funcs->atomic_begin(&crtc->base);
>
> for_each_intel_plane(dev, plane) {
> @@ -4213,6 +4215,8 @@ static void _intel_crtc_disable_planes(struct intel_crtc *crtc)
> }
>
> crtc_funcs->atomic_flush(&crtc->base);
> +
> + /* we'll defer watermark update to after the pipe has been disabled */
> }
>
> void hsw_enable_ips(struct intel_crtc *crtc)
> --
> 2.0.5
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
