On 03/06/2015 10:14 AM, Ville Syrjälä wrote: > On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote: >> On 03/05/2015 11:19 AM, ville.syrjala@xxxxxxxxxxxxxxx wrote: >>> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> I wonder if we should be warning if the wm values we end up with exceed >> the mask size (the fact that you write them with a shift and mask made >> me think of it), but that could be a follow on, or even put into the >> calc code instead. Anyway that's something we can do later after all >> the atomic changes hit. > > IIRC we always have enough bits up to any legal FIFO size, so the clamping > done by vlv_compute_wm() should be enough. I should double check that though > since that isn't the case on a bunch of the other platforms. > > I think in general I'd really like magic register bitfield macros that > scream whenever we overflow something by accident. But that's a much > bigger topic. For one we'd have to parametrize all the macros rather than > using raw shifts. Yeah and that would have the added benefit of more readability. Something for another day if/when we see underruns due to failed wm programming in the future. :) > >> >> Does this fix any of our underrun bugs? Should it have any references: >> lines? > > Those should probably be at the DDR DVFS disable patch since before that > pretty much anything can happen. I was too lazy to trawl bugzilla though. > Pretty much hoping QA can just go retest all display bugs once we get > this landed. Ok, sounds good. Thanks, Jesse _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
