From: Deepak S <deepak.s@xxxxxxxxxxxxxxx> We update the GT PM interrupts mask at the end of set rps. We observed even though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP interrupts before interrupts mask. These extra interrupts are simply wasting cpu cycles. In this patch we mask the interrupts for given freq before requesting new frequency. Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2e1ed07..bbfe4f0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3879,12 +3879,12 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), "Odd GPU freq value\n")) val &= ~1; + + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); if (val != dev_priv->rps.cur_freq) vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); - I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); - dev_priv->rps.cur_freq = val; trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
