On Wed, Mar 04, 2015 at 08:11:38PM +0530, Purushothaman, Vijay A wrote:
> On 2/27/2015 12:31 AM, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > The current minimum vco frequency leaves us with a gap in our supported
> > frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a
> > pixel clock of 241.5 MHz, which is just withing that gap. Reduce the
> > allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz,
> > and thus allow such displays to work.
> >
> > 4.8 GHz is actually the documented (at least in some docs) limit of the
> > PLL, and we just picked 4.86 GHz originally because that was the lowest
> > value produced by the PLL spreadsheet, which obviously didn't consider
> > 2560x1440 displays.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 102b12d..d437a21 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> > * them would make no difference.
> > */
> > .dot = { .min = 25000 * 5, .max = 540000 * 5},
> > - .vco = { .min = 4860000, .max = 6700000 },
> > + .vco = { .min = 4800000, .max = 6700000 },
> > .n = { .min = 1, .max = 1 },
> > .m1 = { .min = 2, .max = 2 },
> > .m2 = { .min = 24 << 22, .max = 175 << 22 },
>
> Minor nitpick: typo in patch title
Dang. I already fixed a typo there before sending this out, but turns
out I only managed to cchange it into a different typo :( Maybe I need
to invest in a spell checker...
>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@xxxxxxxxxxxxxxx>
>
> Thanks,
> Vijay
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--
Ville Syrjälä
Intel OTC
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