2015-03-02 15:20 GMT-03:00 Damien Lespiau <damien.lespiau@xxxxxxxxx>:
> I was dumping the DDI translation tables to make sure my patch updating
> the HDMI entry was doing the right thing when I noticed that the table
> was showing reset values after DPMS.
>
> And indeed, the DDI translation registers are in power well 1 on SKL,
> and so we're losing their values when shutting down eDP.
>
> Calling intel_prepare_ddi() on PW1 enabling re-programs the table.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0898550..0ed1287 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -223,8 +223,10 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
> 1 << PIPE_C | 1 << PIPE_B);
> }
>
> - if (power_well->data == SKL_DISP_PW_1)
> + if (power_well->data == SKL_DISP_PW_1) {
> + intel_prepare_ddi(dev);
> gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
> + }
> }
>
> static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> --
> 1.8.3.1
>
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--
Paulo Zanoni
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