Gen8 Onwards use 48 bit addressing for src and dst base addresses. This patch fixes this for destination base address. Signed-off-by: Praveen Paneri <praveen.paneri@xxxxxxxxx> --- tests/gem_bad_blit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c index b467ba8..593167c 100644 --- a/tests/gem_bad_blit.c +++ b/tests/gem_bad_blit.c @@ -85,6 +85,8 @@ bad_blit(drm_intel_bo *src_bo, uint32_t devid) OUT_BATCH(0); /* dst x1,y1 */ OUT_BATCH((64 << 16) | 64); /* 64x64 blit */ OUT_BATCH(BAD_GTT_DEST); + if (batch->gen >= 8) + OUT_BATCH(BAD_GTT_DEST >> 32); /* Upper 16 bits */ OUT_BATCH(0); /* src x1,y1 */ OUT_BATCH(src_pitch); OUT_RELOC_FENCED(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
