On Tue, 2015-02-24 at 18:10 +0200, Ville Syrjälä wrote:
> On Wed, Feb 18, 2015 at 07:31:18PM +0530, akash.goel@xxxxxxxxx wrote:
> > From: Akash Goel <akash.goel@xxxxxxxxx>
> >
> > Added support for SKL in the 'i915_frequency_info' debugfs function
> >
> > v2: Added missing conversion to 50MHZ for reqf & cagf (Damien)
> >
> > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 25 +++++++++++++++++--------
> > 1 file changed, 17 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 9af17fb..5fb0121 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1089,7 +1089,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> > seq_printf(m, "Current P-state: %d\n",
> > (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> > } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> > - IS_BROADWELL(dev)) {
> > + IS_BROADWELL(dev) || IS_GEN9(dev)) {
> > u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
> > u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> > u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> > @@ -1108,11 +1108,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> >
> > reqf = I915_READ(GEN6_RPNSWREQ);
> > - reqf &= ~GEN6_TURBO_DISABLE;
> > - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > - reqf >>= 24;
> > - else
> > - reqf >>= 25;
> > + if (IS_GEN9(dev)) {
> > + reqf >>= 23;
> > + /* Convert to 50 MHZ units from 16.667 MHZ */
> > + reqf /= GEN9_FREQ_SCALER;
> > + } else {
> > + reqf &= ~GEN6_TURBO_DISABLE;
> > + if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > + reqf >>= 24;
> > + else
> > + reqf >>= 25;
> > + }
> > reqf = intel_gpu_freq(dev_priv, reqf);
> >
> > rpmodectl = I915_READ(GEN6_RP_CONTROL);
> > @@ -1128,7 +1134,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> > rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
> > if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> > - else
> > + else if (IS_GEN9(dev)) {
> > + cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> > + cagf /= GEN9_FREQ_SCALER;
> > + } else
> > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>
>
> I would put gen9 first, then hsw/bsw, then gen6.
>
> Also there's now a gt_act_freq_mhz_show() that needs some love too.
Thanks, will update the gt_act_freq_mhz_show() also.
>
> > cagf = intel_gpu_freq(dev_priv, cagf);
> >
> > @@ -1152,7 +1161,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> > pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
> > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> > seq_printf(m, "Render p-state ratio: %d\n",
> > - (gt_perf_status & 0xff00) >> 8);
> > + (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
> > seq_printf(m, "Render p-state VID: %d\n",
> > gt_perf_status & 0xff);
> > seq_printf(m, "Render p-state limit: %d\n",
> > --
> > 1.9.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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