On Fri, Feb 13, 2015 at 10:27:53AM -0600, jeff.mcgee@xxxxxxxxx wrote: > From: Jeff McGee <jeff.mcgee@xxxxxxxxx> > > The exit from SKL render power gating may not fully restore > slice and EU components. We have to explicitly restore them to > full enablement through the Render Power Clock State register. > > Jeff McGee (3): > drm/i915/skl: Determine SKL slice/subslice/EU info > drm/i915/skl: Add SKL HW status to SSEU status > drm/i915: Request full SSEU enablement on Gen9 All merged to dinq, thanks. -Daniel > > drivers/gpu/drm/i915/i915_debugfs.c | 80 +++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_dma.c | 73 +++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 11 ++++- > drivers/gpu/drm/i915/i915_reg.h | 44 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_lrc.c | 47 +++++++++++++++++++++- > 5 files changed, 252 insertions(+), 3 deletions(-) > > -- > 2.2.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
