On 18/02/15 11:48, Thomas Daniel wrote: > As of Gen6, the general purpose area of the hardware status page has shrunk and > now begins at dword 0x30. i915 driver uses dword 0x20 to store the seqno which > is now reserved. So shift our HWSP dwords up into the general purpose range > before this bites us. > > Signed-off-by: Thomas Daniel <thomas.daniel@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index b6c484f..39183fc 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring, > * 0x06: ring 2 head pointer (915-class) > * 0x10-0x1b: Context status DWords (GM45) > * 0x1f: Last written status offset. (GM45) > + * 0x20-0x2f: Reserved (Gen6+) > * > - * The area from dword 0x20 to 0x3ff is available for driver usage. > + * The area from dword 0x30 to 0x3ff is available for driver usage. > */ > -#define I915_GEM_HWS_INDEX 0x20 > -#define I915_GEM_HWS_SCRATCH_INDEX 0x30 > +#define I915_GEM_HWS_INDEX 0x30 > +#define I915_GEM_HWS_SCRATCH_INDEX 0x40 > #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) > > void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf); Well, nothing much can go wnorg here! Reviewed-by: Dave Gordon <david.s.gordon@xxxxxxxxx> But just FYI, these will all get changed again when we add support for preemption (: because then we'll need more than one place to store 'sequence numbers' :) .Dave. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
