The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
Cc: Linus Walleij <linus.walleij@xxxxxxxxxx>
Cc: Alexandre Courbot <gnurou@xxxxxxxxx>
Cc: Thierry Reding <thierry.reding@xxxxxxxxx>
Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dsi.c | 35 +++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dsi.h | 11 +++++++++++
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c8c8b24..6b56ca0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -31,6 +31,7 @@
#include <drm/drm_panel.h>
#include <drm/drm_mipi_dsi.h>
#include <linux/slab.h>
+#include <linux/gpio.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
@@ -415,6 +416,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
+ /* Panel Enable over CRC PMIC if needed */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)
+ gpio_set_value_cansleep(
+ intel_dsi->crc_base + GPIO_PANEL_EN, 1);
+
+ msleep(intel_dsi->panel_on_delay);
+
/* Disable DPOunit clock gating, can stall pipe
* and we need DPLL REFA always enabled */
tmp = I915_READ(DPLL(pipe));
@@ -432,8 +440,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
/* put device in ready state */
intel_dsi_device_ready(encoder);
- msleep(intel_dsi->panel_on_delay);
-
drm_panel_prepare(intel_dsi->panel);
for_each_dsi_port(port, intel_dsi->ports)
@@ -576,6 +582,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
msleep(intel_dsi->panel_off_delay);
msleep(intel_dsi->panel_pwr_cycle_delay);
+
+ /* Panel Disable over CRC PMIC if needed */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)
+ gpio_set_value_cansleep(
+ intel_dsi->crc_base + GPIO_PANEL_EN, 0);
}
static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -977,6 +988,12 @@ static const struct drm_connector_funcs intel_dsi_connector_funcs = {
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
+static int match_gpio_chip_by_label(struct gpio_chip *chip,
+ void *data)
+{
+ return !strcmp(chip->label, data);
+}
+
void intel_dsi_init(struct drm_device *dev)
{
struct intel_dsi *intel_dsi;
@@ -1070,6 +1087,20 @@ void intel_dsi_init(struct drm_device *dev)
goto err;
}
+ /*
+ * In case of BYT with CRC PMIC, we need to use GPIO for
+ * Panel control. Store the GPIO base
+ */
+ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
+ struct gpio_chip *gpio;
+ gpio = gpiochip_find(GPIO_CHIP_NAME, match_gpio_chip_by_label);
+ if (!gpio) {
+ printk("Failed to find crc gpio chip\n");
+ intel_dsi->crc_base = 0;
+ } else
+ intel_dsi->crc_base = gpio->base;
+ }
+
intel_encoder->type = INTEL_OUTPUT_DSI;
intel_encoder->cloneable = 0;
drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..31074a7 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -29,6 +29,14 @@
#include <drm/drm_mipi_dsi.h>
#include "intel_drv.h"
+/* CRC PMIC GPIO Access */
+#define GPIO_CHIP_NAME "gpio_crystalcove"
+#define GPIO_BACKLIGHT_EN 94
+#define GPIO_PANEL_EN 95
+
+#define PPS_BLC_PMIC 0
+#define PPS_BLC_SOC 1
+
/* Dual Link support */
#define DSI_DUAL_LINK_NONE 0
#define DSI_DUAL_LINK_FRONT_BACK 1
@@ -44,6 +52,9 @@ struct intel_dsi {
struct intel_connector *attached_connector;
+ /* base for GPIOs from CRC chip */
+ int crc_base;
+
/* bit mask of ports being driven */
u16 ports;
--
1.9.1
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