On Fri, Feb 06, 2015 at 08:26:33PM +0530, akash.goel@xxxxxxxxx wrote:
> From: Akash Goel <akash.goel@xxxxxxxxx>
>
> On SKL, the frequency programmed in RPNSWREQ (A008) register
> has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> function, as per this change.
>
> Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> ---
Right, we suppose here that val in in 16.66 Mhz units. At the very least
we need update the trace point:
trace_intel_gpu_freq_change(val * 50);
Then val is passed to gen6_rps_limits(). The values of 0xA014 are also
in 16.66 Mhz units, so that part is fine, but the fields of that
register have changed a bit so we also need to update gen6_rps_limits()
for gen9 (if not done by a later patch).
--
Damien
> drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bebefe7..58c8c0e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3764,7 +3764,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
> if (val != dev_priv->rps.cur_freq) {
> gen6_set_rps_thresholds(dev_priv, val);
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_GEN9(dev))
> + I915_WRITE(GEN6_RPNSWREQ,
> + GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
> + else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> I915_WRITE(GEN6_RPNSWREQ,
> HSW_FREQUENCY(val));
> else
> --
> 1.9.2
>
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