From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Here's the second part of my CHV display fixes pile. There are some really
weird things going on with the PHY, and this series includes whatever
workaround I managed to invent to overcome those issues.
The lane stagger setup I just gleaned from one of the docs, although I'm
not sure the magic numbers are even correct anymore. So not sure if it
helps with anything really. And the cmnlane glue revert is just to save a
bit more power when only one PHY is needed.
Ville Syrjälä (4):
drm/i915: Implement chv display PHY lane stagger setup
drm/i915: Add a hack to fix link training errors on pipe A+port B on
CHV
Revert "drm/i915: Hack to tie both common lanes together on chv"
drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++++-
drivers/gpu/drm/i915/intel_dp.c | 58 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_hdmi.c | 35 ++++++++++++++++++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 38 ++++++++++++---------
5 files changed, 138 insertions(+), 21 deletions(-)
--
2.0.5
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