On Thu, 05 Feb 2015, Shobhit Kumar <shobhit.kumar@xxxxxxxxx> wrote:
> LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case
> of dual link. In the dual link implementation, the bit is correctly set
> or unset for hardcoded PORT_A, but for bit update the register base value
> is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will
> read base value from PORT_C and program for PORT_A. Mostly in case of dual
> link all other bit values should be same, but logically we should read from
> PORT_A. So hardcode to read initial value from PORT_A as well.
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar@xxxxxxxxx>
Pushed to drm-intel-next-fixes, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 6857d19..3fe8a1e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -177,12 +177,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
> I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> usleep_range(2500, 3000);
>
> - val = I915_READ(MIPI_PORT_CTRL(port));
> -
> /* Enable MIPI PHY transparent latch
> * Common bit for both MIPI Port A & MIPI Port C
> * No similar bit in MIPI Port C reg
> */
> + val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
> usleep_range(1000, 1500);
>
> @@ -360,10 +359,10 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> == 0x00000), 30))
> DRM_ERROR("DSI LP not going Low\n");
>
> - val = I915_READ(MIPI_PORT_CTRL(port));
> /* Disable MIPI PHY transparent latch
> * Common bit for both MIPI Port A & MIPI Port C
> */
> + val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
> usleep_range(1000, 1500);
>
> --
> 1.9.1
>
--
Jani Nikula, Intel Open Source Technology Center
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