From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
The DP spec has nothing at all to say about double clocked modes. One
might assume they don't exist, and if you think about the concept
doesn't make much sense since the link already runs at higher fixed
frequency. So let's drop the DRM_MODE_FLAG_DBLCLK checks and simply
use the mode as if it was not double clocked.
I've tested this on a Dell UP2414Q which claims to support 720x576i
and 720x480i double clocked CEA modes, and it seems perfectly happy
with both modes using the 1x clock.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index eea9e36..4b0dadb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -222,9 +222,6 @@ intel_dp_mode_valid(struct drm_connector *connector,
if (mode->clock < 10000)
return MODE_CLOCK_LOW;
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return MODE_H_ILLEGAL;
-
return MODE_OK;
}
@@ -1189,9 +1186,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_connector->panel.fitting_mode);
}
- if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
- return false;
-
DRM_DEBUG_KMS("DP link computation with max lane count %i "
"max bw %02x pixel clock %iKHz\n",
max_lane_count, bws[max_clock],
--
2.0.5
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