On Tue, Jan 27, 2015 at 09:44:01PM +0000, Chris Wilson wrote: > On Tue, Jan 27, 2015 at 03:58:05PM +0100, Daniel Vetter wrote: > > On Mon, Jan 26, 2015 at 10:47:10AM +0000, Chris Wilson wrote: > > > An interesting bug occurs on Pineview through which the root cause is > > > that the writes of the PTE values into the GTT is not serialised with > > > subsequent memory access through the GTT (when using WC updates of the > > > PTE values). This is despite there being a posting read after the GTT > > > update. However, by changing the address of the posting read, the memory > > > access is indeed serialised correctly. > > > > > > Whilst we are manipulating the memory barriers, we can remove the > > > compiler :memory restraint on the intermediate PTE writes knowing that > > > we explicitly perform a posting read afterwards. > > > > > > v2: Replace posting reads with explicit write memory barriers - in > > > particular this is advantages in case of single page objects. Update > > > comments to mention this issue is only with WC writes. > > > > > > Testcase: igt/gem_exec_big #pnv > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88191 > > > Tested-by: huax.lu@xxxxxxxxx (v1) > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > > Cc: Daniel Vetter <daniel.vetter@xxxxxxxx> > > > > Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx> > > > > Shouldn't we Cc: stable@xxxxxxxxxxxxxxx too? > > Yes, if we can narrow down a user bug it fixes, definitely. Right makes sense, so meanwhile queued for next only. -Daneil -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
