From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Follow the sequence in the BIOS spec and clear the RC_CONTROL register before changing any of the other RC6/RP registers. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b73d601..e7f0f21 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4712,6 +4712,9 @@ static void cherryview_enable_rps(struct drm_device *dev) * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + /* Disable RC states. */ + I915_WRITE(GEN6_RC_CONTROL, 0); + /* 2a: Program RC6 thresholds.*/ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ @@ -4801,6 +4804,9 @@ static void valleyview_enable_rps(struct drm_device *dev) /* If VLV, Forcewake all wells, else re-direct to regular path */ gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + /* Disable RC states. */ + I915_WRITE(GEN6_RC_CONTROL, 0); + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); I915_WRITE(GEN6_RP_UP_EI, 66000); -- 2.0.5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
