On Tue, Jan 13, 2015 at 12:46:53PM -0800, Kenneth Graunke wrote: > This is an important optimization for avoiding read-after-write (RAW) > stalls in the HiZ buffer. Certain workloads would run very slowly with > HiZ enabled, but run much faster with the "hiz=false" driconf option. > With this patch, they run at full speed even with HiZ. > > Increases performance in OglVSInstancing by about 2.7x on Braswell. > > Signed-off-by: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> also for the remaining two patches. > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > 1 file changed, 5 insertions(+) > > Split, as requested by Ben. > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 0df15a4..23020d6 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -846,6 +846,11 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) > HDC_FORCE_NON_COHERENT | > HDC_DONOT_FETCH_MEM_WHEN_MASKED); > > + /* According to the CACHE_MODE_0 default value documentation, some > + * CHV platforms disable this optimization by default. Turn it on. > + */ > + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > + > /* Improve HiZ throughput on CHV. */ > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); > > -- > 2.2.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
