Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
On Fri, Jan 9, 2015 at 12:56 PM, Vandana Kannan
<vandana.kannan@xxxxxxxxx> wrote:
> Definition of VLV RR switch bit and corresponding toggling in
> set_drrs function.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++--
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 40ca873..63a3fca 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3840,6 +3840,7 @@ enum punit_power_well {
> #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
> #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
> #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
> +#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
> #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
> #define PIPECONF_BPC_MASK (0x7 << 5)
> #define PIPECONF_8BPC (0<<5)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 85a029e..3362d93 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4819,10 +4819,16 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
> reg = PIPECONF(intel_crtc->config.cpu_transcoder);
> val = I915_READ(reg);
> if (index > DRRS_HIGH_RR) {
> - val |= PIPECONF_EDP_RR_MODE_SWITCH;
> + if (IS_VALLEYVIEW(dev))
> + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val |= PIPECONF_EDP_RR_MODE_SWITCH;
> intel_dp_set_m_n(intel_crtc);
> } else {
> - val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> + if (IS_VALLEYVIEW(dev))
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> + else
> + val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
> }
> I915_WRITE(reg, val);
> }
> --
> 2.0.1
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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