On Wed, Dec 17, 2014 at 03:19:02PM +0000, Dave Gordon wrote: > On some generations of chips, it is necessary to read an MMIO register > before getting the sequence number from the status page in main memory, > in order to ensure coherency; and on all generations this should be > either helpful or harmless. > > In general, we want this operation to be the cheapest possible, since > we require only the side-effect of DMA completion and don't interpret > the result of the read, and don't require any coordination with other > threads, power domains, or anything else. > > However, finding a suitable register may be problematic; on GEN6 chips > the ACTHD register was used, but on VLV et al access to this register > requires FORCEWAKE and therefore many complications involving spinlocks > and polling. > > So this commit introduces this synchronising operation as a distinct > vfunc in uncore, so that it can be GEN- or chip-specific if needed. > > For now, a sample 'universal' implementation is provided which just > reads the TAIL register of the render engine, this being a register > which should always be accessible on all GENs without requiring > forcewake or other complications. TAIL requires forcewake. Don't make this an uncore function, it is an implementation detail of the engine. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
