On Mon, Dec 15, 2014 at 04:59:42PM +0200, Jani Nikula wrote: > On Fri, 12 Dec 2014, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > On Wed, Dec 10, 2014 at 02:00:02PM -0800, Jesse Barnes wrote: > >> Should address a warning reported in #79824. > >> > >> References: https://bugs.freedesktop.org/show_bug.cgi?id=79824 > >> Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > > > > Isn's this fixed by https://freedesktop.org/patch/37900/ ? > > Off-topic, does that link really work for you? Yes > > Jani. > > > > > > >> --- > >> drivers/gpu/drm/i915/intel_display.c | 4 +++- > >> 1 file changed, 3 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >> index c424c36..a19544b 100644 > >> --- a/drivers/gpu/drm/i915/intel_display.c > >> +++ b/drivers/gpu/drm/i915/intel_display.c > >> @@ -1607,7 +1607,9 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > >> BUG_ON(INTEL_INFO(dev)->gen >= 5); > >> > >> /* PLL is protected by panel, make sure we can write it */ > >> - if (IS_MOBILE(dev) && !IS_I830(dev)) > >> + if (IS_MOBILE(dev) && !IS_I830(dev) && > >> + (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || > >> + intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) > >> assert_panel_unlocked(dev_priv, crtc->pipe); > >> > >> /* Enable DVO 2x clock on both PLLs if necessary */ > >> -- > >> 1.9.1 > >> > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Technology Center -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
