On Thu, Dec 11, 2014 at 03:20:39PM +0000, Tvrtko Ursulin wrote:
>
> On 12/11/2014 12:28 PM, sonika.jindal@xxxxxxxxx wrote:
> >From: Sonika Jindal <sonika.jindal@xxxxxxxxx>
> >
> >We were incorreectly bypassing the flush everytime which led to fifo
> >underrun when more than one plane is enabled.
> >
> >Signed-off-by: Sonika Jindal <sonika.jindal@xxxxxxxxx>
> >---
> > drivers/gpu/drm/i915/intel_pm.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 5748bf9..8cd045a 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
> > skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
> > skl_wm_flush_pipe(dev_priv, pipe, 2);
> > intel_wait_for_vblank(dev, pipe);
> >+ reallocated[pipe] = true;
> > }
> >-
> >- reallocated[pipe] = true;
> > }
> >
> > /*
>
> Works like a charm now!
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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